module tyrc_core(/*GEN_PORT*/
//output port  /*GEN_LINK START*/
//input port
clk,rst_n
/*GEN_LINK END*/
);

localparam ADDR_WD = 8;
localparam WORD_WD = 8;
localparam SEL1_WD = 5;
localparam SEL2_WD = 3;
//GEN_INPUT
/*GEN_LINK START*/
input clk;
input rst_n;
/*GEN_LINK END*/
//GEN_OUTPUT
/*GEN_LINK START*/
/*GEN_LINK END*/
//GEN_WIRE
/*GEN_LINK START*/
wire [ADDR_WD-1:0]addr;
wire [WORD_WD-1:0]bus1;
wire inc_pc;
wire [WORD_WD-1:0]instruction;
wire load_add_r;
wire load_ir;
wire load_pc;
wire load_r0;
wire load_r1;
wire load_r2;
wire load_r3;
wire load_reg_y;
wire load_reg_z;
wire [WORD_WD-1:0]mem_rdata;
wire mem_wr_en;
wire [SEL1_WD-1:0]mux_sel_to_bus1;
wire [SEL2_WD-1:0]mux_sel_to_bus2;
wire zero_flag;
/*GEN_LINK END*/

/*tyrc_ctrl_path u_ctrl LINK_MODULE
*/
//tyrc_ctrl_path u_ctrl(/*GEN_LINK*/); GEN_LINK_ADD
/*GEN_LINK START*/
tyrc_ctrl_path u_ctrl(
    //output port inst
    .load_add_r(load_add_r),
    .mem_wr_en(mem_wr_en),
    .load_reg_y(load_reg_y),
    .load_reg_z(load_reg_z),
    .mux_sel_to_bus2(mux_sel_to_bus2),
    .load_r2(load_r2),
    .load_r3(load_r3),
    .inc_pc(inc_pc),
    .load_r1(load_r1),
    .mux_sel_to_bus1(mux_sel_to_bus1),
    .load_r0(load_r0),
    .load_pc(load_pc),
    .load_ir(load_ir),
    //input port inst
    .rst_n(rst_n),
    .zero_flag(zero_flag),
    .instruction(instruction),
    .clk(clk)
);
/*GEN_LINK END*/

/*tyrc_proc_path u_proc LINK_MODULE
*/
//tyrc_proc_path u_proc(/*GEN_LINK*/); GEN_LINK_ADD
/*GEN_LINK START*/
tyrc_proc_path u_proc(
    //output port inst
    .bus1(bus1),
    .zero_flag(zero_flag),
    .instruction(instruction),
    .addr(addr),
    //input port inst
    .rst_n(rst_n),
    .load_ir(load_ir),
    .clk(clk),
    .load_reg_y(load_reg_y),
    .mem_rdata(mem_rdata),
    .load_reg_z(load_reg_z),
    .mux_sel_to_bus2(mux_sel_to_bus2),
    .load_r2(load_r2),
    .load_r3(load_r3),
    .inc_pc(inc_pc),
    .load_r1(load_r1),
    .mux_sel_to_bus1(mux_sel_to_bus1),
    .load_r0(load_r0),
    .load_pc(load_pc),
    .load_add_r(load_add_r)
);
/*GEN_LINK END*/

/*mem_sram u_mem LINK_MODULE
.addr_in(addr),
.data_in(bus1),
.data_out(mem_rdata),
.write_en(mem_wr_en),
*/
//mem_sram u_mem(/*GEN_LINK*/); GEN_LINK_ADD
/*GEN_LINK START*/
mem_sram u_mem(
    //output port inst
    .data_out(mem_rdata),//FROM .data_out(mem_rdata)
    //input port inst
    .rst_n(rst_n),
    .write_en(mem_wr_en),//FROM .write_en(mem_wr_en)
    .data_in(bus1),//FROM .data_in(bus1)
    .addr_in(addr),//FROM .addr_in(addr)
    .clk(clk)
);
/*GEN_LINK END*/

endmodule
//SUB MODULE LIST START
//"./"
//SUB MODULE LIST END
